The invention relates generally to system controller design for computer systems and, more particularly but not by way of limitation, to a device and method for tagging memory access requests with information identifying a characteristic of the system controller or requesting device.
In personal computer systems (PCs) communication between various devices coupled to different buses and access to system memory is mediated by a single bridge or system controller circuit. Many bridge circuits also facilitate the maintenance of cache coherency operations by routing requests for access to system memory to a specified bus before relaying the request to memory. To fulfill these operational roles, the electrical and functional complexity of bridge circuits has increased dramatically.
As the complexity of bridge circuit designs have increased it has become more difficult to troubleshoot (debug) the resulting devices. Often times, invasive techniques to extract signals representing the internal state of these devices must be obtained to facilitate system development and troubleshooting efforts. In addition, as the number, type and operational speed of devices seeking access to system memory increases conventional bridge circuits may fail to provide the necessary memory access bandwidth required.
Accordingly, it would be beneficial to provide a mechanism to aid system designers during the debug phase of bridge circuit development. It would also be beneficial to provide a mechanism to aid and improve the processing of memory access requests.
In one embodiment the invention provides a method to process memory access request signals. The method includes receiving a memory access request signal from a device, tagging the memory access request signal to indicate a characteristic associated with the memory access request signal, and presenting the tagged memory access request signal to a bus. Illustrative characteristics include, but are not limited to, information indicative of a state of the system controller (e.g., memory request queue length) and the identity of the device issuing the memory access request signal (e.g., as a burst or non-burst oriented device). The method may also include using the information encoded in the tag to augment or modify memory access operations of a memory control unit. In another embodiment, the invention provides a system controller apparatus to implement the method.